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Written by Aparna Joshi   

Let's see what's Final Test Data...Also known as Packaged Parts Test Data...


How is this generated? Once an individual die is cut from the wafer and packaged, it goes under testing. This is called final testing. This is the final product which will be sold to the customer. It is very important to test the chip in its final package. These are tested individually. A DUT board or load board is designed to test the chip. These boards have one or more test sites. Multi-site boards have capacity to test more than one part at a time. In this case, site id is also logged in the data. The data that tester generates is normally huge. It is not uncommon to have 300-500 tests for each part. There can be 10,000 or more parts in one lot. One can imagine how big the data file can grow into. It also creates bin summary data along with the parametric data.

What does it contain? This data contains the results of functional test parameters, pin failures and conditional data such as capacitance discharge over the time and binning information.

What is a format? As there is a wide range of testers available, formats vary. Main format is STDF (Standard Test Data Format). It is a binary format. Why? because it is very efficient for a tester to log humongous amount of data in less time. ASCII format takes more time to log as hardware i/o efficiency plays major role in this. Teradyne, Credence Verigy testers always log data in STDF. HP84000 testers log in ASCII format called as ATDF (ASCII Test Data Format). Most of the analysis tools provide STDF readers. Binning information is used to see yield quickly. Some companies choose to log data in a CSV format (Comma Separated Values) format. It has its cost in terms of time. Binary format is the fastest way to log data but needs a parser to read.

What is a usage? Hmmm... For possible yield loss issues, packaging defects detection and for analysis of parts returned by customers (RMA) are main uses of this data. This is the first data set that shows various modules working together in case of multi-module chips. It is essential to test an integrated functionality of the chip before it gets shipped.

If a particular lot is showing low yield, it is sent for retesting to rule out any measurement errors. Sometimes, yield gets recovered during retesting. The data can be compared against the historical data to pin point the yield loss problems. This data is correlated with wafer probe data. To track down what wafers are used to make this final chip, lot genealogy data is essential. In fact, tracking down wafers for packaged parts is called as Lot Genealogy.

Failed devices/parts are not shipped to customers. That's why yield is very crucial at this stage. Particularly, when wafer probe yield is very high and packaged part yield is low, creates a huge pressure on yield engineers to resolve yield loss issues. This data is very useful in nailing the yield loss issues.

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